Journal of Emerging Trends in Artificial Intelligence

Boon Chong Ang is a Tech Lead at Intel, Malaysia, with extensive experience in ASIC design, artificial intelligence, customer engineering, and semiconductor technologies. He holds a Bachelor's degree in Electronic and Electrical Engineering and an MBA, and is pursuing a Doctor of Business Administration. He is a Senior Member of IEEE (SMIEEE) and actively contributes to international standards committees, conference organization, editorial boards, and humanitarian initiatives. His professional expertise spans ASIC methodology, AI-assisted chip design, verification, and semiconductor innovation.

• Artificial Intelligence in Semiconductor Design
• ASIC Design and Verification
• Machine Learning Applications
• Electronic Design Automation (EDA)
• System-on-Chip (SoC) Methodologies

• Senior Member, IEEE (SMIEEE)
• IEEE P1800 Committee Member
• IEEE Verilog-AMS Committee Member
• JEDEC Solid State Memory Committee Member
• IEEE Circuits and Systems Society Member
• IEEE Internet of Things Community Member
• IEEE Consumer Electronics Society Member
• Editorial Board Member, IJAET Journal
• Program Chair and Session Chair for multiple IEEE international conferences
• Keynote Speaker and Invited Industrial Speaker
• Standards contributor to IEEE P3405, P1450.1, and P1800 initiatives

• 2023 IEEE ISIEA – Implementation Tool Machine Learning Features Evaluation (Intel)
• 2023 IEEE ICET – Pre-silicon ASIC Library Validation (Intel)
• 2023 IEEE CASS Korea-Malaysia Membership Development Workshop – ASIC Pre-silicon Qualification Methodology
• 2022 SEACAS (Hanoi) – Design Scalability with AI Assist
• 2022 IEEE ICET – Clock Optimization Techniques (Best Presenter Award)
• 2022 IEEE ICCSS – A Simplified Flop MTBF Extraction Methodology
• 2022 IEEE ICEEE – Automated IRDrop ECO
• 2022 IEEE ICCCAS – Automated Chip MTBF Calculator
• 2021 IEEE ICM – Design Space Optimization With Machine Learning Library Pruning
• 2021 Design & Reuse – Performance Auto Sweep
• 2021 IEEE ICECS – Hybrid MultiSource Clock Tree Synthesis
• 2021 IEEE ICECIT – Clock Domain Crossing Verification Challenges (Best Presenter Award)
• 2020 Technovate (AI Category) – Problematic Cell Auto Pruning
• 2018 RISC-V Workshop, IIT Madras – From RISC-V Spec to 22FFL Silicon
• 2017 ARIEET – Dynamic Performance Estimator
• 2014 SG-SNUG – Automated Interface Timing Checkers
• 2014 ICCSS – Standard Cell Transistor Level ATPG Coverage
• 2014 ISMS – Product Level MTBF Calculation
• 2014 ICOCS – Gate Strength Aware DC Coverage Improvement
• 2013 IEEE ICE-ID – Custom Logic ATPG Modeling
• 2013 HCTL Special Edition (Invited Paper) – Hold Time Improvement With Dynamic Dual Power Zone and Useful Active Load Technique On Sequential Cell
• 2013 UPM Invited Industrial Speaker – ASIC Methodology Overview
• 2013 SG-SNUG – Parametric On-Chip Variation Analysis
• 2013 IEEE AIMS – Unified Padring Design Flow: New Development And Results
• 2013 IEEE CICSyN – Unified Padring Design Flow
• 2013 IEEE TENCON – ASIC Design Margin Methodology
• 2013 IEEE ISMS – ASIC Clock Tree Estimation In Design Planning
• 2012 IEEE ICCAS – ASIC Leakage Performance Area Trade Off Analysis
• 2012 IEEE ICSE – Gross Die Estimator's Caveats For ASIC Floorplanning
• 2012 SG-SNUG – Top 10 STA Tidbits
• 2012 SG-SNUG – Mesh Clock Delay Characterizations With CustomSim-XA
• 2012 UK-SNUG – None-Rectilinear FRAM Generation
• 2012 Germany SNUG – CTMesh or CTS
• 2012 France SNUG – ASIC Compliance CTMesh Solution
• 2012 IMECS – MCP_Or_Not_MCP
• 2012 SJ-SNUG – Oh Boy, Chip Area Blows-Up Again!
• 2011 Design & Reuse – Wirebond Power Bus Watch Outs
• 2011 SG-SNUG – 10 SPEF Extraction Watch Out
• 2011 SG-SNUG – FPGA Power Modeling Methodology (PTPX)
• 2011 SG-SNUG – Double Switching Noise
• 2010 SG-SNUG – Optimal Decoupling Cap Placement Analysis
• 2009 SG-SNUG – Power Switch Insertion Analysis
• 2008 SG-SNUG – CCS vs NLDM in 45nm Designs
• 2008 SG-SNUG – Noise Modeling in 45nm Designs
• 2002 IEEE ICSE – Pass Transistor Logic ALU Design